FIG. 1 is an exemplary schematic diagram of a capacitor 100 in accordance with the prior art. The capacitor 100 includes a first plate 110, a first electrode 115 coupled to the first plate and permitting interconnection with other circuit elements (not shown in FIG. 1), a second plate 120 together with a second electrode 125 coupled to the second plate 120 and a dielectric 130 disposed between the first 110 and second 120 plates of the capacitor 100. The capacitor 100 operates by storing and releasing charge in response to signals coupled to the first 115 and second 125 electrodes. It is generally desirable to form capacitors 100 together with CMOS circuit elements but without requiring modification of standard CMOS processes. This allows greater choice of foundry for CMOS IC manufacturing, simplifies production, and reduces expense in realizing ICs that include the capacitor 100.
Some applications for capacitors 100 require larger breakdown voltages than are needed for most of the other circuit elements forming the IC. Such applications may include power supplies associated with programming circuitry for programmable or nonvolatile memory elements.
The first 110 and second 120 plates may be realized in a number of forms in ICs using standard CMOS processes. These forms can include metal or semiconductor layers comprising the capacitor plates 110, 120, separated by a layer forming the dielectric 130, or interdigitated conductive patterns comprising the capacitor plates 110, 120.
Capacitors 100 formed using interdigitated conductive patterns for the capacitor plates 110, 120 tend to provide relatively high breakdown voltage. These also tend to be relatively large and to provide relatively little capacitance per unit area of the IC in which they are formed.
Capacitors 100 may also be formed by using a first conductive plate 110, which may be relatively planar, formed on or in a substrate, a relatively planar dielectric 130 disposed atop the first plate 110 and a relatively planar second conductive plate 120 formed on and supported by the dielectric layer 130. The first plate 110 may be formed from metal or from a conductively doped semiconductive layer. When formed on a semiconductive substrate using conventional CMOS processing techniques and employing a dielectric analogous to a FET gate dielectric, such capacitors may be referred to as MOS capacitors or MDS (metal-dielectric-semiconductor) capacitors, although the dielectric may or may not be an oxide or silicon dioxide, and the first 110 and second 120 plates may be semiconductive or other conductive material rather than including metal.
For example, first 110 and second 120 plates may be formed using polysilicon or metal layers separated by a dielectric layer 130 formed using polyimide or an oxide such as silicon dioxide. Such capacitors 100 may be formed to have relatively high breakdown voltage using a relatively thick dielectric layer 130 but then provide relatively little capacitance per unit surface area of the IC because of the thickness of the dielectric layer 130.
Alternatively, MDS structures may be formed either as FETs or as MDS capacitors, using the same material for the dielectric 130 as is used to form gate dielectrics for other FET structures that are also part of the IC. This allows the capacitor 100 to be formed via the same processes that are employed to form transistors and the like. However, gate dielectrics are typically made relatively thin because, among other things, the transconductance of a FET per unit gate width (i.e., per unit area of the IC) decreases as the gate dielectric thickness increases. As a result, while use of dielectric layers 130 that are also suitable for FET gate structures provides relatively high capacitance per unit area, the breakdown voltage of the resulting capacitor 100 is relatively low.
Various prior art capacitors have been employed to address these conflicting aspects of high-voltage capacitor realization. For example, U.S. Pat. No. 5,187,637, entitled “Monolithic High-Voltage Capacitor” and issued to Embree describes a capacitor employing multiple dielectric layers and a guard ring but requires process steps not normally associated with CMOS IC fabrication, while U.S. Pat. No. 5,587,869 entitled “High-Voltage Capacitor Manufacturing Method And High-Voltage Capacitor” and issued to Azumi et al. describes a high-voltage capacitor not suitable for monolithic integration.
Various prior art capacitors have been employed to address the conflicting aspects of high-voltage capacitor realization in the context of CMOS ICs. For example, U.S. Pat. No. 6,137,153, entitled “Floating Gate Capacitor For Use In Voltage Regulators”, issued to Le et al. describes a single floating-gate NMOS transistor used together with other circuitry as a constant-capacitance capacitor in a voltage-divider structure for voltage regulation, while U.S. Pat. No. 6,262,469, entitled “Capacitor For Use In A Capacitive Divider That Has A Floating-Gate Transistor As A Corresponding Capacitor” and issued to Le et al. describes one or more floating-gate NMOS transistors used together with other circuitry to provide a capacitive voltage divider for voltage regulation. These circuits are not intended to provide high-voltage capacitors; they also require a conventional control gate disposed atop the floating gate in order to operate, but the processing required to fabricate such control-gate structures is not available in many modem CMOS foundry processes.
One approach that has been employed to address these conflicting aspects of high-voltage capacitor realization in CMOS ICs is to stack a pair of FETs with source/drain contacts connected together, or a pair of MOS capacitors, in series by forming each capacitor structure so that they share a contact in the form of a well of semiconductive material. FIG. 2 is an exemplary schematic diagram of a high-voltage capacitor 200 formed from two MOS capacitor structures 205 and 210, in accordance with the prior art. For example, U.S. Pat. No. 5,926,064, entitled “Floating Gate MOS Capacitor” and issued to Hariton describes a voltage-independent capacitor circuit analogous to that of FIG. 2 and describes the associated biasing circuitry required for such.
Each of the MOS capacitor structures 205 and 210 of FIG. 2 is illustrated as comprising a PMOS FET-like structure having a respective externally accessible capacitor electrode 212, 214, a floating gate 231 and control electrode 232, source/drain electrodes or power electrodes 215, a channel 220 electrically coupling the source/drain electrodes 215 of each structure 205 or 210, and a body or well contact 225. In each of the structures 205 or 210, the gate structure includes a dielectric 230 such as a conventional gate oxide, and is capacitively coupled to the source/drain electrodes 215 and channel 220 through the dielectric 230.
Each FET structure 205, 210 is shown as comprising a floating-gate electrode 231 formed on a first portion of the dielectric layer 230 and a control-gate electrode, 232, formed on and separated from the floating-gate electrode 231 by a second portion of the dielectric layer 230. Conventional floating-gate transistors incorporate separate floating gate 231 and control gate 232 structures, with only the control gate 232 typically being electrically accessible.
A conventional stacked capacitor 200 is formed by interconnecting one of the source/drain contacts 215 from each of the FETs at a common intercapacitor node 235 and employing the control-gate electrodes 212 and 214, respectively, as the first 115 and second 125 capacitor electrodes (FIG. 1). One issue with such stacked capacitors 200 is that conventional MOS or floating-gate transistor structures have no means for adjusting charge on common node 235, and, consequently, are unable to avoid one of the two structures 205, 210 carrying a disproportionate amount of the voltage impressed across the electrodes 212, 214.
Furthermore, the semiconductive structure forming the common source/drain region has leakage currents associated with it. As a result, a bias circuit (not illustrated) is required in order to maintain the intercapacitor node 235 voltage and to provide a path for addition or removal of charge caused by leakage currents. Requiring such bias circuitry for each high-voltage capacitor 200 undesirably increases the complexity of the resulting integrated circuit that includes the high-voltage capacitors 200 and results in poorer form factor, i.e., a larger circuit layout.
Accordingly, improved techniques and structures are needed for realizing high-voltage capacitors having a compact form factor using standard CMOS processes.